The present invention relates to slack reduction, and more specifically, to slack redistribution for additional power recovery.
In computer-aided design (CAD) of system-on-chip (SoC) designs of integrated circuits (chips), a logical or circuit design is converted to a physical realization through processes that include synthesis, placement, and routing. As part of the synthesis process, technology-independent logic synthesis is converted to technology mapping with standard cell library elements. A cell is a component placed within the chip. The technology mapping (synthesis) phase, as well as the placement and routing of the selected components, may be done iteratively to ensure that timing and other design constrains are met.